When designing the LSI using CAD (Computer Aided Design), internal delay times of the LSI used for timing analysis or the like may be categorized into a gate delay and a net delay. The gate delay refers to a delay time of a signal propagating through a gate, that is, a circuit element. On the other hand, the net delay refers to a delay time of a signal propagating through a wiring. Generally, the gate delay may be calculated using a library that is characterized by an input waveform distortion (or slew) and an output load capacitance. On the other hand, the net delay may be calculated according to various kinds of calculating methods.
A first calculating method restrictively calculates the delay time in a narrow range by instructing a high-precision calculation for each case in which the high accurate calculation is preferable. A second calculating method calculates the delay time by a single calculating method depending on a tradeoff between the accuracy of the delay time and the calculation cost, when performing the calculation with respect to all nets of the LSI. The calculation cost refers to a cost that takes into consideration a processing time (or calculation time), a memory capacity preferred by the process (or calculation), and the like.
On the other hand, a third calculating method extracts a C (capacitance) model and a RC (resistance-capacitance) model when extracting a stray capacitance, and calculates the delay time by using a calculation formula that is suited for each model depending on a wiring length. However, the accuracy of the third calculating method may be insufficient with respect to the most recent microtechnology. In addition, the third calculating method does not calculate the delay time by taking into consideration an inductance. Furthermore, the calculation of the delay time using the C model and the RC model may generate a relatively large calculation error. For example, when one of the C model and the RC model is selected depending solely on the wiring length, a different model may be selected depending on a difference of 0.01 μm between the wiring lengths of the models, for example. As a result, even though the two nets are essentially the same in appearance, the delay time that is calculated by the calculation formula may greatly differ depending on the model that is selected.
A fourth calculating method categorizes the nets of the entire LSI into normal nets and bus nets, for example, and the delay time for the bus nets is calculated using a calculation formula suited for the bus nets.
A fifth calculating method uses an Elmore delay model, in order to simply obtain the delay time from the wiring resistance and the wiring capacitance by approximation. A sixth calculating method uses an AWE (Asymtotic Waveform Evaluation) in order to obtain a response waveform with respect to an input step voltage by approximation. According to the sixth calculating method, the calculation accuracy becomes higher as the order of the solution becomes higher, however, the calculation cost greatly increases as the order of the solution becomes higher.
A seventh calculating method uses a PRIMA (Passive Reduced-order Interconnect Macromodeling Algorithm) that solves a determinant representing a circuit formula (or equation) by reducing elements of the determinant. However, according to the seventh calculating method, the calculation accuracy becomes higher as the order of the solution becomes higher, however, the calculation cost greatly increases as the order of the solution becomes higher.
Recently, the microtechnology of the high-speed LSI may prefer the calculation accuracy of the net delay time to be further improved. In addition, the number of nets in the entire LSI is extremely large due to the increase in the design scale. In the recent LSI having the increased design scale, the number of gates or the number of wiring nets may exceed 10,000,000. For this reason, when the high-precision calculating method is used with respect to all of the nets of the LSI, the calculation time to calculate the delay time becomes extremely long an impractical.
Hence, although there are various proposed methods to calculate the delay time of the net within the LSI, the calculation cost increases when the delay time is to be calculated with a high accuracy. Accordingly, it is difficult to calculate the delay time of the net in the circuit with a high accuracy.
Examples of the related art include Japanese Laid-Open Patent Publications No. 7-182380, No. 6-60145, and No. 3-220676, and A. Odabasioglu, M. Celik, and T. Pileggi, “PRIMA: passive reduced-order interconnect macromodeling algorithm”, ICCAD 1997, pp. 58-65.